1. Field
Example embodiments relate to a semiconductor device and method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device having a differential gate dielectric layer and a related semiconductor device.
2. Description of Related Art
Prompted by the high integration of today's semiconductor devices, research into integrating a large number of devices within a restricted space is being conducted. A conventional planar transistor includes a gate electrode disposed on a semiconductor substrate, and source and drain regions disposed in the semiconductor substrate contacting both sides of the gate electrode. Reducing the size of the gate electrode reduces the distance between the source and drain regions, and thus, reduces an effective channel length. Such a reduction in the effective channel length may cause a short channel effect, which deteriorates active switching characteristics of a device. Also, the reduced size of the gate electrode and source and drain regions may degrade current drivability. Thus, there is a limit in increasing the integration of planar transistors. In order to overcome the above problems, research into a recessed channel transistor and method of fabricating the same is underway.